Lots of electronic products are oriented to be portable, multi-functional and slim with the development of electronic technology, but it is also referred to that the functions and the included circuit devices collocated in electronic products are increased, more complicated and more elegant. However, even the lithographic processes used in the formation of integrated circuit (IC) with very-large-scale-integration (VLSI) achieve to nano-level limits of 45 nm, 32 nm or less, vigorous development for three-dimensional chip stacking technology is promoted in order to integrate more abundant amount of ICs within the limited chip area.
Please refer to FIG. 1, which illustrates a diagram showing the stacking technology for the three dimensional chip in the prior art. In FIG. 1, a plurality of core chips 101a, 101b, . . . 101n are electrically connected with each other by the contact portions 11 and the through connection elements 12 (i.e. electrodes). Each of core chips 101a, 101b, . . . 101n further can be electrically connected to the circuit chip 100 by the metal connection 30, so as to transmit or receive the control signals. The circuit chip 100 (i.e. interposer) further is electrically connected to other external circuit by the external terminal 103. The plurality of core chips 101a, 10b, . . . 101n in FIG. 1 are vertically stacked with the contact portions 11, which are electrically connected to each of core chips 101a, 101b, . . . 101n by the through connection elements 12. The above-mentioned illustration is the stacked three-dimensional chip in the prior art, and information regarding the chip stacking technology in the prior art can be referred to U.S. Patent Application No. 2007/0132085 A1.
Nowadays, art of semiconductor is oriented towards minimization. However, defects of the aforementioned stacking technology would be generated as illustrated follows. The dimensions of the contact portions 11 and the through connection elements 12 (shown in FIG. 1) will be minimized to nano size with the minimization of the critical dimension. If 1) the alignment within each of core chips 101a, 101b, . . . 101n is shifted; 2) the positions of the through connection elements 12 generate errors in the chip manufacturing processes; or 3) the positions of the contact portions 11 generate errors in the stacking process, the contact portions 11 will not be precisely and electrically connected to the through connection elements 12, so that the stacked three-dimensional chips cannot normally work and be an imperfection.
It is therefore attempted by the applicant to deal with the above situation encountered in the prior art.